`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:49:35 03/31/2014 
// Design Name: 
// Module Name:    scoring 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module scoring(clk, rand1, rand2, rand3, rand4, M1, M2, M3, M4,
 button, column, score);
	 
	 input clk;
	 input [3:0] rand1, rand2, rand3, rand4;
	 input [9:0] M1, M2, M3, M4;
	 input button;
	 input [2:0] column;
	 output reg score;
	 
	always @(posedge clk) begin
	
		if(M1>=410 && M1<=450) begin
			if(button==1 && rand1[column]==1)begin
				score = 1;
			end else begin
				score = 0;
			end
		end
		
		if(M2>=410 && M2<=450) begin
			if(button==1 && rand2[column]==1)begin
				score = 1;
			end else begin
				score = 0;
			end
		end
		
		if(M3>=410 && M3<=450) begin
			if(button==1 && rand3[column]==1)begin
				score = 1;
			end else begin
				score = 0;
			end
		end
		
		if(M4>=410 && M4<=450) begin
			if(button==1 && rand4[column]==1)begin
				score = 1;
			end else begin
				score = 0;
			end
		end
		

		
	end
	
endmodule
